The present invention relates generally to dielectrically isolated intergrated circuits and more specifically to an improved dielectrically isolated intergrated circuit.
Support base can induce large depleted regions in high resistivity dielectrically isolated islands. The size of the depleted regions is dependent on bias voltage. They can interact with components in the islands, altering such characteristics as breakdown voltage and leakage current.
A known method which eliminates support bias influence on component characteristics is use of a wrap-around buried layer 16, 18 which is present adjacent all parts of the isolation oxide 14 as illustrated in FIG. 1. The layers used in the prior art were developed originally to minimize series resistance introduced by the high resistivity island 12, which includes surface contact region 22. They were then applied in situations where shielding from substrate bias was desired. These layers, typically having a peak doping impurity concentration greater than 1.times.10.sup.18 ions per cubic centimeter and a thickness of about 10 microns, eliminate the bias effect by providing sufficient impurity concentration to terminate for positive substrate bias or to act as a source for negative substrate bias all field lines induced by the substrate bias.
The presence of the buried layer along the island side walls results in several problems. Components in the island must be spaced further from its edge than would be the case were the side wall layer not there. The spacing requirement arises both from the need to have junctions not overlap the side wall layer and from the need for a sufficient space to be maintained between any PN junction and the side wall layer to permit the desired breakdown voltage to be attained.
A device built in a dielectrically isolated island 12 having only a buried layer 16 is illustrated in FIG. 2. Junctions intended to have the same voltage capability in the two types of islands are illustrated in FIGS. 1 and 2. In many cases the spacing of a PN junction 20, 12 from the island edge must be increased by more than a factor of two to accommodate a side wall layer. One method to increase density in the chip is selectively forming the side wall layer for those devices which require collector resistance or connection to the buried layer. This is illustrated in U.S. Pat. No. 4,290,831 to Ports et al.
Reduction of breakdown voltage due to high fields induced by conductors lying above the side wall layer to island high-low junction is another problem which results from a side buried layer. There are known solutions to the problem such as very thick oxide over the junction, an extra doped surface layer which broadens the high-low transition region or field plates between the conductor and the high-low junction. They all require extra process complication and often require extra area, both of which increase cost.
An object of the present invention is to provide a wrap-around layer which shields components in a dielectrically isolated island from support bias effects without introducing the problems of the conventional wrap-around layer.
Another object is to provide a method of eliminating support bias influence on dielectrically isolated components without requiring extra process complication and extra area.
Yet another further object is to provide a dielectrically isolated island which is optimized for support influence elimination and packing density.
Still another object is to provide a support bias influence elimination structure which allows conductors to run over the edge of the island without inducing breakdown.
These and other objects are provided by using a shield layer of the same conductivity type as the dielectrically isolated islands adjacent the dielectric isolation and extending along the sides thereof having an impurity concentration sufficient to eliminate the support bias influence without seriously affecting the PN junction in the island. The impurity concentration of the shield region is greater than the impurity concentration of the island and less than 1.times.10.sup.13 ions per square centimeter. The peak impurity concentration, which is adjacent the dielectric isolation, should be less than 5.times.10.sup.16 ions per centimeter cubed. The shield layer along the bottom of the island may have the same impurity concentration as the side of the island or may have a greater impurity concentration. The impurity concentration of the shield region is higher than the impurity concentration of the dielectrically isolated island and lower than the impurity concentration of a region of opposite conductivity type formed in the dielectrically isolated island.
The side walls which are optimized for eliminating the support biasing effect is also applicable to device regions which are dielectrically isolated on the side walls and junction isolated on the bottoms.
The method of forming the shield region of the present invention controls the impurity concentration during the formation of the buried and side regions of the original island prior to the formation of the dielectric isolation layer to achieve the total concentration and peak concentration described above.